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Datasheet File OCR Text:

om .c 4U et he aS at .D w w SCSI Bus Expander Family w SYM53C120 SCSI Bus Expander SYM20101 Extender Board SYM20102 Converter Board
Supports Single-Ended(SE)-to-SE or (SE)-to-Differential Modes
m o .c U t4 e e h S ta a .D w w w
PRELIMINARY Data Manual and User's Guide Version 3.0
SCSI SE-SE
INCREASING SCSI RELIABILITY ACTIVE
TolerANT
(R)
NEGATION TECHNOLOGY
T14971I
om .c 4U et he aS at .D w w w
The product described in this publication is a licensed product of Symbios Logic. TolerANT is a registered trademark of Symbios Logic. Wolfpack is a registered trademark of Microsoft Corporation.
It is the policy of Symbios Logic to improve products as new technology, components, software, and firmware become available. Symbios Logic, therefore, reserves the right to change specifications without notice.
The products in this manual are not intended for use in life-support appliances, devices, or systems. Use of these products in such applications without the written consent of the appropriate Symbios Logic officer is prohibited.
Copyright (c)1996-1997 By Symbios Logic Fort Collins, Colorado U.S.A. All Rights Reserved Printed in U.S.A.
We use comments from our readers to improve Symbios Logic product literature. Please e-mail any comments regarding technical documentation to pubs@symbios.com.
PRELIMINARY
Preface
Preface
This manual provides description and electrical characteristics of the SYM53C120 SCSI Bus Expander chip which supports single-ended to single-end SCSI bus expansion (Extender) or single-ended to differential SCSI bus conversion (Converter). This manual also provides a description of and how to install the SYM20101 Extender board and the SYM20102 Converter board. Both boards use the SYM53C120 SCSI Bus Expander chip. This manual assumes some prior knowledge of current and proposed SCSI standards. For background information, please contact: ANSI 11 West 42nd Street New York, NY 10036 (212) 642-4900 Ask for document number X3.131-1994 (SCSI-2) (SCSI-3) Global Engineering Documents 15 Inverness Way East Englewood, CO 80112 (800) 854-7179 or (303) 792-2181 (outside U.S.) Ask for document number X3.131-1994 (SCSI-2) or X3.253 (SCSI-3 Parallel Interface) ENDL Publications 14426 Black Walnut Court Saratoga, CA 95070 (408) 867-6642 Document names: SCSI Bench Reference, SCSI Encyclopedia Prentice Hall Englewood Cliffs, NJ 07632 (201) 767-5937 Ask for document number ISBN 0-13-796855-8, SCSI: Understanding the Small Computer System Interface Symbios Logic Electronic Bulletin Board (719) 573-3562 SCSI Electronic Bulletin Board (719) 574-0424 Symbios Logic World Wide Web http://www.symbios.com (See EPI (Enhanced Parallel Interface) Specification for expander configurations)
SYM53C120 Data Manual and SYM2010x Boards
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PRELIMINARY
Revision Record
Revision Record
Page No. All All All All Date 10/96 11/96 1/97 2/97 Version 1.0 2.0 2.1 2.2 Remarks Preliminary Data Manual Complete Data Manual Changed DIFF_MODE to DIFF_MODE/ and modified SCSI Interface Timings Title changed to SYM53C120 SCSI Bus Expander. DC Characteristics, TolerANT Technology Electrical Characteristics and Differential Wiring Diagram changed. This manual now includes the SYM2010x boards Timing changes in Chapter 4 Added Chapter 5, SYM2010x SCSI Boards
Manual Title 4-1, 2, 3, 4, and 8 All of Chapter 5
6/97
3.0
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SYM53C120 Data Manual and SYM2010x Boards
PRELIMINARY
Contents
Contents
Chapter 1
Introduction
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Scalable Device Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 SCSI Bus Electrical Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Chapter 2
Functional Description
Interface Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 SCSI A-Side and B-Side Single-Ended Control Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Re-timing Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Precision Delay Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 State Machine Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Differential Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Data and Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Busy (BSY) Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Request (REQ)/Acknowledge (ACK) Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Reset (RST) Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Control/Data (C/D), Input/Output (I/O), Message (MSG) and Attention (ATN) Controls . . . . . . . . . . . . 2-4 Select (SEL) Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Differential Direction Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Differential Mode (DIFF_MODE/) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Differential Sense (DIFF_SENSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Clock (CLOCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Chip Reset (RESET/) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Warm Start Enable and Transfer Active (WS_ENABLE and XFER_ACTIVE) . . . . . . . . . . . . . . . . . . . . . . . 2-6 Chapter 3
Signal Descriptions
SYM53C120 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 SYM53C120 Signal Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 SCSI A Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 SCSI B Single-ended Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 SCSI B Differential Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Control Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
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Contents
Chapter 4
Electrical Characteristics
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 TolerANT Technology Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 SCSI Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Chapter 5
SYM20101/2 Boards
SYM20101/2 Circuit Board Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal, Atmospheric Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electromagnetic Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Safety Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operational Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYM20101 Extender Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Board Mounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Board Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Connector J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCSI Connectors J2 and J3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Termination Control Connector J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LEDs and Connector J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYM20101 Extender Board Installation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mount Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connect Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYM20102 Converter Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Board Mounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Board Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Connector J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCSI Connectors J2 and J3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Termination Control Connector J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LEDs and Connector J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYM20102 Converter Board Installation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mount Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connect Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5-1 5-1 5-1 5-2 5-2 5-2 5-2 5-2 5-2 5-3 5-3 5-4 5-4 5-4 5-4 5-4 5-5 5-5 5-6 5-6 5-6 5-6 5-6 5-7 5-7 5-8 5-8 5-8 5-8 5-8 5-9 5-9
5-10 5-10 5-10 5-10 5-10
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Contents
Appendix A
Mechanical Drawings
SYM53C120 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Appendix B
Differential Wiring Diagram
SYM53C120 Differential Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Glossary Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Glossary-1 Index Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index-1
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SYM53C120 Data Manual and SYM2010x Boards
PRELIMINARY
Introduction General Description
Chapter 1
Introduction
General Description
The SYM53C120 SCSI Bus Expander is a single chip solution allowing the extension of device connectivity and/or cable length limits of the SCSI bus. The SYM53C120 operates as a SCSI bus expander when multiple single-ended to single-ended cables are connected together while being electrically isolated from each other. The SYM53C120 also operates as a SCSI bus converter when single-ended to differential cables are connected together while being electrically isolated from each other. The SYM53C120 operates in two modes: single-ended to single-ended (Extender Mode) or single-ended to differential (Converter Mode). For applications requiring SE to Low Voltage Differential (LVD), use the SYM53C141 Bus Expander. Table 1-1 shows all modes of operation.
Table 1-1: Mode of Operation Symbios Product SYM53C120 SYM5353C141 Extender SE to SE SE to SE Converter SE to HVD SE to LVD
The SYM53C120 is based upon bus expander technology resulting in some signal filtering and re-timing to maintain signal skew budgets. In addition, the SYM53C120 has no programmable registers, therefore, it does not require any software.
(A-Side) Single-ended Wide Ultra SCSI Bus (Data and Control)
(B-Side) Single-ended Wide Ultra SCSI Bus (Data and Control) OR (B-Side) Differential Wide Ultra SCSI Bus (Data and Control)
SYM53C120 SCSI Bus Expander
Control Signals
40 MHz Oscillator
Figure 1-1: SYM53C120 SCSI Bus Device
Features
s
Accepts any asynchronous or synchronous data transfer rates up to the 40 MB/s rate of Wide Ultra SCSI Targets and initiators can connect to either the SCSI A- or SCSI B-side of the SYM53C120 Does not consume a SCSI ID Can cascade up to three SYM53C120s in series Requires 40 MHz input clock Supports two modes of operation
s s
In both SCSI Bus Extender and Converter modes, cable segments are electrically isolated from each other. This feature maintains the signal integrity of each cable segment. For bus isolation applications, the SYM53C120 is ideally suited for the SYM53C875 Ultra SCSI controller. The SYM53C120 provides additional control capability through the pin level electrical isolation mode. This feature permits logical disconnection of both the A-side bus and the B-side bus without disrupting SCSI transfers currently in progress. For example, devices on the logically disconnected B-side can be swapped out while the A-side bus remains active.
s
s s s s
Single-ended to Single-ended Mode Single-ended to Differential Mode (with external transceivers)
s
Connects two wide and/or narrow SCSI buses
SYM53C120 Data Manual and SYM2010x Boards
1-1
Introduction Application Examples
PRELIMINARY
s
s
Extends Ultra SCSI cable lengths in certain applications Extends total number of connected Ultra SCSI devices supported
for external differential transceivers. The SYM53C120 provides additional control capability through the pin level SCSI bus disable mode. This feature allows logical disconnection of both the A-side bus and B-side bus without disrupting transfers currently in progress. For example, this feature allows electrical disconnection of devices on the B-side to be swapped out while the A-side bus remains active. As with all of Symbios Logic's SYM53C7xx and SYM53C8xx SCSI products, the SYM53C120 features TolerANT(R) technology. The benefits of TolerANT include increased immunity to noise, better performance due to balanced duty cycles, and improved SCSI transfer rates.
s s s s s
Supports TolerANT(R) active negation technology Complete support for SCSI-1, -2, and -3 Completely independent of software Pin level SCSI bus disable mode Packaged in a 128 PQFP
The SYM53C120 SCSI Bus Expander works with Symbios Logic's extensive SYM53C7xx and SYM53C8xx family of SCSI products. It also works with other industry SCSI controllers, disk drives, and SCSI peripherals. Advantages of the SYM53C120 are that it does not require any software or consume a SCSI ID. This allows for easy integration and maximum bus utilization. Adding the SYM53C120 to a SCSI bus environment creates a low risk solution for applications requiring scalable device connectivity and SCSI bus electrical isolation. Figure 1-1 illustrates the connectivity of the SYM53C120 SCSI Bus Expander device. A SCSI singleended(SE) bus connects directly to the SCSI A-side. The interface signals are SCSI bus compatible driver and receiver signals with no internal termination. The SCSI B-side has the single-ended capable driver and receiver and also provides the individual driver controls
Application Examples
The following examples are typical applications for the SYM53C120 SCSI Bus Expander. Many other configurations are possible and are only limited by the imagination of the system architect.
Scalable Device Connectivity
Figure 1-2 illustrates how to use the SYM53C120 to increase the number of devices to 15 on a 3 meter Ultra SCSI bus cable.
Disk Subsystem
Single-ended (3 meters)
Ultra SCSI Host Adapter
Terminator
SYM53C120
SYM53C120
SYM53C120
Single-ended (1.5 meters)
Single-ended (1.5 meters)
Device 5
Device 10
Device 15
Ultra SCSI Drive Box
Ultra SCSI Drive Box
Ultra SCSI Drive Box
Figure 1-2: SCSI Extender Application (Single-Ended to Single-Ended Mode of Operation)
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SYM53C120 Data Manual and SYM2010x Boards
Single-ended (1.5 meters)
SYM53C8xx Ultra SCSI Controller Device 0
Device 1
Device 6
Device 11
PRELIMINARY
Introduction Application Examples
Figure 1-3 illustrates both single-ended to single-ended, and single-ended to differential modes of the
SYM53C120 to create a redundant remote storage configuration.
Dual Channel Ultra SCSI Host Adapter SYM53C876 Dual Channel Ultra SCSI Controller Devices 0 & 1
Differential (25 meters)
Differential Transceivers
Differential Transceivers SYM53C120
Terminator
Single-ended (3 meters) SYM53C120 Differential Transceivers SYM53C120 SYM53C120 Differential Transceivers SYM53C120
Device 12 Single-ended (1.5 meters)
Device 7
Single-ended (1.5 meters)
Device 2
Single-ended (1.5 meters)
Device 14
Device 11
Device 6
Ultra SCSI Remote Storage Box
Ultra SCSI Drive Box Ultra SCSI Drive Box
Figure 1-3: SCSI Extender or Converter Application (Single-Ended to Differential Mode of Operation)
SYM53C120 Data Manual and SYM2010x Boards
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Introduction Application Examples
PRELIMINARY
SCSI Bus Electrical Isolation
Figure 1-4 illustrates how to use the SYM53C120 to electrically isolate an external SCSI bus from an internal SCSI bus. This configuration ensures externally attached peripherals will not affect the operation of internal peripherals.
Internal Ultra SCSI Bus
H.D. 68 pin
H.D. 68 pin
Terminator Terminator SYM53C120
External SCSI Bus (Legacy Devices)
Flash ROM
SYM53C8xx Ultra SCSI Controller PCI Bus
Figure 1-4: SCSI Bus Electrical Isolation
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SYM53C120 Data Manual and SYM2010x Boards
PRELIMINARY
Functional Description Interface Signal Descriptions
Chapter 2
Functional Description
Interface Signal Descriptions
The SYM53C120 has no programmable registers; therefore, no software requirements. SCSI control signals control all SYM53C120 functions. This chapter describes all signals, their groupings and functions. Following is a diagram of the SYM53C120 device divided into the following blocks:
s
SYM53C120 needs to know which side is driving the signals so it can enable the proper drivers to pass the signals along. In addition, the SYM53C120 does some signal re-timing to maintain the signal skew budget from source bus to load bus as if the source was a local bus member.
SCSI A-Side and B-Side Single-Ended Control Blocks that contain TolerANT(R) Drivers and Receivers Re-timing Circuit Precision Delay Control State Machine Control Differential Control
SCSI A-Side and B-Side Single-Ended Control Blocks
In the single-ended to single-ended mode, the SCSI Aside pins are connected internally to the corresponding SCSI B-side pins, forming bi-directional connections to the SCSI bus. The SCSI A-side and B-side single-ended control blocks connect to both targets and initiators and accept any asynchronous or synchronous data transfer rates up to the 40 MB/s rate of Wide Ultra SCSI. TolerANT technology is part of the SCSI A-side and B-side singleended control blocks.
s s s s
(A-Side)
(B-Side)
TolerANT Drivers and Receivers
Single-ended Wide Ultra SCSI Bus
TolerANT Drivers and Receivers
Single-ended Wide Ultra SCSI Bus
SCSI Control Block
SCSI Control Block
Re-timing Circuit
TolerANT(R) Drivers and Receivers
The SYM53C120 features TolerANT technology, which includes active negation on the SCSI drivers and input signal filtering on the SCSI receivers. Active negation causes the SCSI Request, Acknowledge, Data, and Parity signals to be actively driven high rather than passively pulled up by terminators. TolerANT receiver technology improves data integrity in unreliable cabling environments, where other devices would be subject to data corruption. TolerANT receivers filter the SCSI bus signals to eliminate unwanted transitions, without the long signal delay associated with RC-type input filters. This improved driver and receiver technology helps eliminate double clocking of data, the single biggest reliability issue with SCSI operations.
Data and Control
Data and Control
Control
Control
or
Precision Delay Control
State Machine Control
(B-Side) Differential Transceiver Control Wide Ultra SCSI Bus Differential Control
Control Signals
40 Mhz Clock Input
Chip Boundary
Figure 2-1: SYM53C120 Block Diagram
In its simplest form, the SYM53C120 passes data and parity from a source bus to a load bus. The side asserting, de-asserting or releasing the SCSI signals is the source side. The simplest model is that the SYM53C120 is just pieces of wire that allow corresponding SCSI signals to flow from side to side. In reality, the
SYM53C120 Data Manual and SYM2010x Boards
2-1
Functional Description Interface Signal Descriptions
PRELIMINARY
The benefits of TolerANT include increased immunity to noise on the de-asserting signal edge, better performance due to balanced duty cycles, and improved SCSI transfer rates. In addition, TolerANT SCSI devices prevent glitches on the SCSI bus at power-up or powerdown, so other devices on the bus are also protected from data corruption.
Differential Control
In the SCSI converter (single-ended to differential) mode, the SCSI A-side pins are connected internally to the corresponding SCSI B-side differential pins, forming bi-directional connections to the SCSI bus.
Re-timing Logic
The SCSI signals, as they propagate from one side of the SYM53C120 to the other side, are processed by logic that re-times the bus signals as needed to guarantee or improve required SCSI timings. This logic is governed by the state machine controls that keep track of SCSI phases, the location of initiator and target devices, and various timing functions. In addition, this logic contains numerous precision delay elements that are periodically calibrated by the precision delay control block in order to guarantee specified timings such as output pulse widths, setup and hold times, and other timings.
Signal Descriptions
Figure 2-2 illustrates the signal groupings of the SYM53C120. A description the of signals follows but for specific signal timings, see AC Characteristics in Chapter 4, Electrical Characteristics.
SYM53C120
A_SD(15-0)/ A_SDP(1-0)/ A_SC_D/ A_SI_O/ SCSI A Data and Control A_SMSG/ A_SREQ/ A_SACK/ A_SBSY/ A_SATN/ A_SSEL/ A_SRST/ B_SD(15-0)/ B_SDP(1-0)/ B_SC_D/ B_SI_O/ B_SMSG/ B_SREQ/ B_SACK/ B_SBSY/ B_SATN/ B_SSEL/ B_SRST/ SCSI B Data and Control
Precision Delay Control
The precision delay control block provides calibration information to the precision delay elements in the re-timing logic block in order to maintain precise timings as signals propagate through the device. As the SYM53C120's operating conditions, such as voltage and temperature, vary over time, the precision delay control block will periodically update the delay settings in the re-timing logic to maintain constant and precise control over bus timings.
B_SD(15-0)/ B_SDP(1-0)/ RESET/ Control Signals WS_ENABLE XFER_ACTIVE B_SC_D/ B_SI_O/ B_SMSG/ B_SREQ/ B_SACK/ B_SBSY/ B_SATN/ B_SSEL/ B_SRST/ Clock Input CLOCK DIFF_MODE/ DIFF_SENSE Transceiver Control SCSI B Differential Control
State Machine Control
The state machine controls keep track of the SCSI bus phase protocol and other internal operating conditions. This block provides signals to the re-timing logic that identifies how to properly handle SCSI bus signal retiming and protocol, based on observed bus conditions.
Figure 2-2: SYM53C120 Signal Grouping
Data and Parity
The signals named A_SD/(15-0, P0, P1) are the data and parity signals from the A-side and B_SD/(15-0, P0, P1) are the data and parity signals from the B-side of the SYM53C120. These signals are sent and received from the SYM53C120 via SCSI compatible driver and
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PRELIMINARY
Functional Description Interface Signal Descriptions
receiver logic designed into the SYM53C120 interface. This logic provides the necessary drive, sense thresholds, and input hysteresis to function correctly in a SCSI bus environment as defined in ANSI Standard for SCSI-1, SCSI-2 and SCSI-3. The SYM53C120 receives data and parity signals and passes them from the source bus to the load bus and provides any necessary edge shifting to guarantee the skew budget for the load bus. Either side of the SYM53C120 can be the source bus or the load bus. The side asserting, de-asserting or releasing the SCSI signals is the source side. The following steps are a part of the SYM53C120 data path.
s
edge is held for a specified time to prevent any signal bounce. The duration is then controlled by the input signal.
s
The next stage has two modes. One mode simply passes data through. The other mode behaves like a large filter. The mode is selected by the current state in the SYM53C120 state machine which tracks SCSI phases. The large filter mode is used where the Busy (BSY) and Select (SEL) sources may switch from side to side. This output is then fed to the output driver which is a pull-down open collector only. A parallel function ensures that bus (transmission line) recovery is ensured for a specified time after the last signal de-assertion on each signal line.
s
Asserted data is accepted from the receiver logic as soon as it is received. Once the clock signal has been received, data is gated from the receiver latch. The path is next tested to ensure data was not driven by the SYM53C120. Valid data needs to be generated by another node on the source bus to be passed through the SYM53C120 to the load bus. The data is then leading edge filtered. The assertion edge is held for a specified time to prevent any signal bounce. The duration is then controlled by the input signal. The next stage is a latch that samples the signal. This provides a stable data window for the load bus. The final stage develops pull-up and pull-down controls for the SCSI I/O logic, including tri-state controls for the pull-up. A parallel function ensures that bus (transmission line) recovery is ensured for a specified time after the last signal de-assertion on each signal line.
s
Request (REQ)/Acknowledge (ACK) Control
A_SACK/, B_SACK/, A_SREQ/ and B_SREQ/ are clock and control signals. Their signal paths contain controls to guarantee minimum pulse width, filter edges, and does some re-timing when used as data transfer clocks. Each signal, REQ and ACK, has paths from A to B and B to A. The received signal goes through the following processing steps before being sent to the opposite bus.
s
s
s
s
The asserted input signal is sensed and forwarded to the next stage if the direction control permits it. The direction controls are developed from state machines that are driven by the sequence of bus control signals. The signal must then pass the test of not being generated by the SYM53C120. In the A to B bus direction, the next stage is a leading edge filter. This ensures that the output will not switch during the specified hold time after the leading edge. The duration of the input signal determines the duration of the output after the hold time. In the B to A direction, the circuit guarantees a minimum pulse. The next stage passes the signal if it is not a data clock. If REQ or ACK is a data clock, it delays the leading edge to improve data output setup times. The duration is again controlled by the input signal. The following stage is a trailing edge signal filter.
s
s
s
Busy (BSY) Control
A_SBSY/ and B_SBSY/ signals are propagated from the source bus to the load bus. These signals go through the following processing.
s
s
The path is tested to be sure the data was not driven by the SYM53C120. Because valid data needs to be generated by another node on the source bus to be passed through the SYM53C120 to the load bus. The data is then leading edge filtered. The assertion
s
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SYM53C120 Data Manual and SYM2010x Boards
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Functional Description Interface Signal Descriptions
PRELIMINARY
When the signal de-asserts, the filter will not permit any signal bounce. The output signal deasserts at the first de-asserted edge of the input signal.
s
Select (SEL) Control
A_SSEL/ and B_SSEL/ are control signals used during bus arbitration and selection. Whichever bus asserts SEL propagates it to the other side. If both signals are asserted at the same time, the A-side receives SEL and sends it to the B-side. The signal goes through the following processing steps.
s
The last stage develops pull-up and pull-down signals with drive and tri-state control. A parallel function ensures that bus (transmission line) recovery is ensured for a specified time after the last signal de-assertion on each signal line.
s
The input signal is blocked if it is being driven by the SYM53C120. The next stage is a leading edge filter. This ensures that the output will not switch for a specified time after the leading edge. The duration of the input signal then determines the duration of the output. A parallel function ensures that bus (transmission line) recovery is ensured for a specified time after the last signal de-assertion on each signal line.
Reset (RST) Control
A_SRST/ and B_SRST/ are also passed from the source to the load bus. These reset signals are processed in the following steps.
s
s
s
The input signal is blocked if it is already being driven by the SYM53C120. The next stage is a leading edge filter. This ensures that the output will not switch for a specified time after the leading edge. The duration of the input signal then determines the duration of the output. A parallel function ensures that bus (transmission line) recovery is ensured for a specified time after the last signal de-assertion on each signal line.
s
Differential Direction Controls
B_SDIR(15-0, P0, P1), B_BSYDIR, B_SELDIR, B_CD_DIR, B_IO_DIR, B_MSGDIR, B_REQDIR, B_ACKDIR, B_ATNDIR and B_RSTDIR are all differential direction control signals on the B-side of the SYM53C120. When the B-side is used in single-ended mode, these signals are not used and should be left unconnected. When the B-side is used in differential mode, these signals are used to control the direction of each external differential transceiver on the B-side interface. Every B-side signal requires a driver enable control to allow for all the possible signal conditions including SCAM support. The data bits require individual controls for the selection phase of SCSI bus protocol.
s
Control/Data (C/D), Input/Output (I/O), Message (MSG) and Attention (ATN) Controls
A_SCD/, A_SIO/, A_SMSG/, A_SATN/, B_SCD/, B_SIO/, B_SMSG/ and B_SATN/ are control signals that have the following processing steps.
s
The input signal is blocked if it is being driven by the SYM53C120. The next stage is a leading edge filter. This ensures that the output will not switch for a specified time after the leading edge. The duration of the input signal then determines the duration of the output. The final stage develops pull-up and pull-down controls for the SCSI I/O logic, including tri-state controls for the pull-up. A parallel function ensures that bus (transmission line) recovery is ensured for a specified time after the last signal de-assertion on each signal line.
s
s
s
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PRELIMINARY
Functional Description Interface Signal Descriptions
Table 2-1: Direction Control Signals (B_SDIR(15-0, P0, P1), B_BSYDIR, B_SELDIR, B_CD_DIR, B_IO_DIR, B_MSGDIR, B_REQDIR, B_ACKDIR, B_ATNDIR and B_RSTDIR) Polarities Signal Level High = 1 Low = 0 State Asserted De-asserted Effect Drive SYM53C120 signals onto Bus B Input Bus B signals to SYM53C120
Table 2-3: DIFF_SENSE Control Signal Polarity
Signal Level High = 1 Low = 0 State Asserted De-asserted Effect The B-side drivers and receivers are enabled B-side Drivers and Receivers are disabled
Clock (CLOCK)
This is the 40 MHz oscillator input to the SYM53C120. This is the clock source for protocol control state machines and timing generation logic. This clock is not used in any bus signal transfer paths.
Differential Mode (DIFF_MODE/)
This input informs the SYM53C120 that external differential transceivers are used in this particular application. In addition, this input causes internal logic to adjust for external differential control. Table 2-2: DIFF_MODE/ Control Signal Polarity
Signal Level Low = 0 State Asserted Effect Differential Signals and Controls are enabled from the SYM53C120 SYM53C120 Bus B drivers function in single-ended mode
Chip Reset (RESET/)
This general chip reset is intended to force all the internal elements of the SYM53C120 into a known state. This will bring all state machines to an idle state and force all controls to a passive state. The minimum RESET input asserted pulse width is 100 nanoseconds. The SYM53C120 also contains an internal Power On Reset (POR) function that is wire ORed with the chip reset pin which eliminates the need for an external chip reset. Table 2-4: RESET/ Control Signal Polarity
Signal Level Low = 0 High = 1 State Asserted De-asserted Effect Reset is forced to all internal SYM53C120 elements SYM53C120 is not in a forced reset state
High = 1
De-asserted
Differential Sense (DIFF_SENSE)
This input signal determines if a single-ended device is placed on the differential bus. If a single-ended source is detected, the differential B-side is disabled and no differential B-side signals are driven. This mechanism prevents potential damage to the differential transceivers.
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Functional Description Interface Signal Descriptions
PRELIMINARY
Warm Start Enable and Transfer Active (WS_ENABLE and XFER_ACTIVE)
These two pins provide additional control capability for the SYM53C120. They allow both the SCSI A-side bus and the SCSI B-side bus to be logically disconnected. The XFER_ACTIVE output changes state only with the detection of a SCSI bus free state; this guarantees that transfers currently in progress will not be disrupted by the assertion or de-assertion of the WS_ENABLE pin. Assertion or de-assertion of the WS_ENABLE pin may not be effective immediately since it may take several milliseconds for a bus free state to be detected and then indicated by a change in state of the XFER_ACTIVE output signal. Table 2-5: WS_ENABLE Signal Polarity
Signal Level High = 1 State Asserted Effect The SYM53C120 will start transfers through the device once the next SCSI bus free is detected until de-assertion. The SYM53C120 will stop transfers through the device when the next SCSI bus free is detected.
Low = 0
De-asserted
Table 2-6: XFER_ACTIVE Signal Polarity
Signal Level High = 1 State Asserted Effect Normal operation, transfers through the SYM53C120 are enabled The SYM53C120 has detected a bus free phase while WS_ENABLE is low disabling transfers through the device.
Low = 0
De-asserted
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PRELIMINARY
Signal Descriptions SYM53C120 Pin Diagram
Chapter 3
Signal Descriptions
The SYM53C120 is packaged in a 128 pin Plastic Quad Flat Pack (PQFP). Detailed descriptions follow, grouped by function.The decoupling capacitor arrangement shown below is recommended to maximize the benefits of the internal split ground system. Capacitor values should be between 0.01 and 0.1 uF.
SYM53C120 Pin Diagram
SCSI B Differential Control NC Vss_IO XFER_ACTIVE NC NC NC Vdd_IO Vdd_CORE NC B_SDIR12 B_SDIR13 B_SDIR14 Vss_CORE Vss_IO B_SDIR15 B_SDIRP1 B_SDIR0 B_SDIR1 Vdd_IO B_SDIR2 B_SDIR3 B_SDIR4 B_SDIR5 Vss_IO B_SDIR6 B_SDIR7 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
NC NC Vdd-SCSI A_SD12/ A_SD13/ A_SD14/ Vss_SCSI A_SD15/ A_SDP1/ A_SD0/ A_SD1/ Vss_SCSI A_SD2/ A_SD3/ A_SD4/ A_SD5/ Vss_SCSI A_SD6/ A_SD7/ A_SDP0/ A_SATN/ Vss_SCSI A_SBSY/ A_SACK/ A_SRST/ A_SMSG/ A_SSEL/ Vss_SCSI A_SCD/ A_SREQ/ A_SIO/ A_SDB8/ Vss_SCSI A_SD9/ A_SD10/ A_SD11/ Vdd_SCSI WS_ENABLE/
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
SCSI A Interface Pins
128 PQFP
SYM53C120 Data Manual and SYM2010x Boards
NC NC Vss_IO NC NC RESET/ Vdd_IO Vdd_CORE CLOCK DIFF_MODE/ DIFF_SENSE Vss_CORE B_SDIR11 B_SDIR10 Vss_IO B_SDIR9 B_SDIR8 B_IO_DIR B_REQDIR Vdd_IO B_CD_DIR B_SELDIR B_MSGDIR B_RSTDIR Vss_IO B_ACKDIR
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
SCSI B Differential Control
Figure 3-1: SYM53C120 Pin Diagram
SCSI B Single-ended Interface Pins
SYM53C120
B_SDIRP0 B_ATNDIR Vdd_SCSI B_SD12/ B_SD13/ B_SD14/ Vss_SCSI B_SD15/ B_SDP1/ B_SD0/ B_SD1/ Vss_SCSI B_SD2/ B_SD3/ B_SD4/ B_SD5/ Vss_SCSI B_SD6/ B_SD7/ B_SDP0/ B_SATN/ Vss_SCSI B_SBSY/ B_SACK/ B_SRST/ B_SMSG/ B_SSEL/ Vss_SCSI B_SCD/ B_SREQ/ B_SIO/ B_SD8/ Vss_SCSI B_SD9/ B_SD10/ B_SD11/ Vdd_SCSI B_BSYDIR
3-1
Signal Descriptions SYM53C120 Signal Grouping
PRELIMINARY
SYM53C120 Signal Grouping
SYM53C120
A_SD(15-0)/ A_SDP(1-0)/ A_SC_D/ A_SI_O/ A_SMSG/ SCSI A Data and Control A_SREQ/ A_SACK/ A_SBSY/ A_SATN/ A_SSEL/ A_SRST/ B_SD(15-0)/ B_SDP(1-0)/ B_SC_D/ B_SI_O/ B_SMSG/ B_SREQ/ B_SACK/ B_SBSY/ B_SATN/ B_SSEL/ B_SRST/ SCSI B Data and Control
B_SD(15-0)/ B_SDP(1-0)/ RESET/ Control Signals WS_ENABLE XFER_ACTIVE B_SC_D/ B_SI_O/ B_SMSG/ B_SREQ/ B_SACK/ B_SBSY/ B_SATN/ B_SSEL/ B_SRST/ Clock Input CLOCK DIFF_MODE/ DIFF_SENSE Transceiver Control SCSI B Differential Control
Figure 3-2: SYM53C120 Functional Signal Grouping
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PRELIMINARY
Signal Descriptions SCSI A Interface Pins
SCSI A Interface Pins
Table 3-1: SCSI A Signal Description SCSI A A_SD/(15-0) Pin 8, 6, 5, 4, 36, 35, 34, 32, 19, 18, 16, 15, 14, 13, 11, 10 9, 20 29 31 26 30 24 23 21 27 25 Type I/O Strength 48 mA Description Data (16-bit SCSI bus)
A_SDP/(1-0) A_SCD/ A_SIO/ A_SMSG/ A_SREQ/ A_SACK/ A_SBSY/ A_SATN/ A_SSEL/ A_SRST/
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
48 mA 48 mA 48 mA 48 mA 48 mA 48 mA 48 mA 48 mA 48 mA 48 mA
Data parity bits Phase line, command/data Phase line, input/output Phase line, message Data handshake signal from target device Data handshake signal from initiator device Bus arbitration signal, busy Attention, the initiator is requesting a message out phase Bus arbitration signal, select device Bus Reset
SYM53C120 Data Manual and SYM2010x Boards
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Signal Descriptions SCSI B Single-ended Interface Pins
PRELIMINARY
SCSI B Single-ended Interface Pins
Table 3-2: SCSI B Signal Description SCSI B B_SD/(15-0) Pin 95, 97, 98, 99, 67, 68, 69, 71, 84, 85, 87, 88, 89, 90, 92, 93 94, 83 74 72 77 73 79 80 82 76 78 Type I/O Strength 48 mA Data (16-bit SCSI bus) Description
B_SDP/(1-0) B_SCD/ B_SIO/ B_SMSG/ B_SREQ/ B_SACK/ B_SBSY/ B_SATN/ B_SSEL/ B_SRST/
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
48 mA 48 mA 48 mA 48 mA 48 mA 48 mA 48 mA 48 mA 48 mA 48 mA
Data parity bits Phase line, command/data Phase line, input/output Phase line, message Data handshake signal from target device Data handshake signal from initiator device Bus arbitration signal, busy Attention, the initiator is requesting a message out phase Bus arbitration signal, select device Bus Reset
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Signal Descriptions SCSI B Differential Interface Pins
SCSI B Differential Interface Pins
Table 3-3: SCSI B Differential Signal Description SCSI B Differential B_SDIR(15-0) Pin 114, 117, 118, 119, 51, 52, 54, 55, 103, 104, 106, 107, 108, 109, 111, 112 113, 102 59 56 61 57 64 65 101 60 62 O Type Strength 4 mA Description Driver direction control for SCSI data line
B_SDIRP(1-0) B_CD_DIR B_IO_DIR B_MSGDIR B_REQDIR B_ACKDIR B_BSYDIR B_ATNDIR B_SELDIR B_RSTDIR
O O O O O O O O O O
4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA
Driver direction control for SCSI parity signals Driver direction control for CD/ Driver direction control for IO/ Driver direction control for MSG/ Driver direction control for REQ/ Driver direction control for ACK/ Driver direction control for BSY/ Driver direction control for ATN/ Driver direction control for SEL/ Driver direction control for RST/
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Signal Descriptions Control Interface Pins
PRELIMINARY
Control Interface Pins
Table 3-4: Chip Control Signal Description Control RESET/ WS_ENABLE XFER_ACTIVE 44 38 126 Pin I I O 16 mA Type Strength Description Master reset, active low Enable/disable SCSI transfers through SYM53C120 Transfers through the SYM53C120 are enabled/disabled
Table 3-5: SCSI Control Signal Description SCSI Control CLOCK DIFF_MODE/ DIFF_SENSE 47 48 49 Pin I I I Type 40 MHz input clock SCSI B-side bus mode control The DIFF_SENSE pin detects the presence of a single-ended device on a differential system. This pin should be tied low during single-ended operation and pulled high during differential operation. Description
Table 3-6: Power and Ground Signal Description Power and Ground VDD-SCSI VSS-SCSI VSS_IO VDD_IO VDD_CORE VSS_CORE 3, 37, 66, 100 7, 12, 17, 22, 28, 33, 70, 75, 81, 86, 91, 96 41, 53, 63, 105, 115, 127 45, 58, 110, 122 46, 121 50, 116 Pin Type I/O I/O I/O I/O CORE CORE Description Power supplies to the SCSI bus I/O pins Power supplies to the SCSI bus I/O pins Power supplies to the I/O pins Power supplies to the I/O pins Power supplies to the CORE logic Power supplies to the CORE logic
Table 3-7: No Connect Pins No Connects NC Require pullups Require pulldown Pin 39, 40, 42, 43, 120, 123, 124 1, 2, 128 125 Type Description No external connection required. Requires a pullup. Requires a pulldown with a 1K ohm resistor.
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Electrical Characteristics DC Characteristics
Chapter 4
Electrical Characteristics
DC Characteristics
Table 4-1: Absolute Maximum Stress Ratings Symbol TSTG VDD VIN ILP* ESD** Parameter Storage temperature Supply voltage Input Voltage Latch-up current Electrostatic discharge Min -55 -0.5 VSS - 0.5 Max 150 7.0 VDD + 0.5 2K Unit Test Conditions MIL-STD 883C, Method 3015.7
C
V V mA V
150
-
Stresses beyond those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions beyond those indicated in the Operating Conditions section of the manual is not implied. * -2V < VPIN < 8V ** SCSI pins only
Table 4-2: Operating Conditions Symbol VDD IDD Parameter Supply voltage Supply current (dynamic) Supply current (static) TA Operating free air Thermal resistance (junction to ambient air) Min 4.75 0 Max 5.25 80 1 70 41.3 Unit V mA mA Test Conditions -
C C/W
JA
Conditions that exceed the operating limits may cause the device to function incorrectly
SYM53C120 Data Manual and SYM2010x Boards
4-1
Electrical Characteristics DC Characteristics
PRELIMINARY
Table 4-3: SCSI Signals - A_SD(15-0)/, A_SDP(1-0)/, A_SREQ/, A_SACK/, B_SD(15-0)/, B_SDP(1-0)/, B_SREQ/, B_SACK/ Symbol VIH VIL VOH* VOL IOZ Parameter Input high voltage Input low voltage Output high voltage Output low voltage Tri-state leakage Min 1.9 VSS - 0.5 2.4 VSS -10 Max VDD + 0.5 1.0 3.5 0.4 10 Unit V V V V Test Conditions 2.5 mA 48 mA -
A
*TolerANT active negation enabled
Table 4-4: SCSI Signals - A_SMSG, A_SI_O/, A_SC_D/, A_SATN/, A_SBSY/, A_SSEL/, A_SRST/, B_SMSG, B_SI_O/, B_SC_D/, B_SATN/, B_SBSY/, B_SSEL/, B_SRST/ Symbol VIH VIL VOL IOZ Parameter Input high voltage Input low voltage Output low voltage Tri-state leakage (SRST/ only) Min 1.9 VSS - 0.5 VSS -10 -500 Max VDD + 0.5 1.0 0.5 10 -50 Unit V V V Test Conditions 48 mA -
A
Table 4-5: Input Signals - CLOCK, DIFF_SENSE, DIFF_MODE/*, WS_ENABLE* Symbol VIH VIL IIN Parameter Input high voltage Input low voltage Input leakage Min 2.0 VSS - 0.5 -10* Max VDD + 0.5 0.8 10 Unit V V Test Conditions -
A
* The minimum (IIN) Input leakage for DIFF_MODE/ and WS_ENABLE is -100 A.
4-2
SYM53C120 Data Manual and SYM2010x Boards
PRELIMINARY
Electrical Characteristics DC Characteristics
Table 4-6: Capacitance Symbol CI CIO Parameter Input capacitance of input pads Input capacitance of I/O pads Min Max 7 Unit pF Test Conditions -
-
10
pF
-
Table 4-7: Differential Signals - B_SDIR(15-0), B_SDIRP0, B_SDIRP1, B_CD_DIR, B_IO_DIR, B_MSGDIR, B_REQDIR, B_B_ACKDIR, B_BSYDIR, B_SELDIR, B_SELDIR, B_RSTDIR Symbol VOH VOL IOZ Parameter Output high voltage Output low voltage Tri-state leakage Min 2.4 VSS -10 Max VDD 0.4 10 Unit V V Test Conditions -4 mA 4 mA -
A
Table 4-8: Control Signals - RESET/ Symbol VIH VIL IOZ Parameter Input high voltage Input low voltage Tristate leakage Min 3.5 VSS - 0.5 -10 Max VDD + 0.5 1.5 10 Unit V V Test Conditions -
A
Table 4-9: Control Signals - XFER_ACTIVE Symbol VOH VOL IOZ Parameter Output high voltage Output low voltage Tri-state leakage Min 2.4 VSS -10 Max VDD 0.4 10 Unit V V Test Conditions 16 mA 16 mA -
A
SYM53C120 Data Manual and SYM2010x Boards
4-3
Electrical Characteristics TolerANT Technology Electrical Characteristics
PRELIMINARY
TolerANT Technology Electrical Characteristics
Table 4-10: TolerANT Technology Electrical Characteristics Symbol VOH
1
Parameter Output high voltage Output low voltage Input high voltage Input low voltage Input clamp voltage Threshold, high to low Threshold, low to high Output high current Output low current Short-circuit output high current Short-circuit output low current Input high leakage Input low leakage Input resistance Capacitance per pin Rise time, 10% to 90% Fall time, 90% to 10% Slew rate, low to high Slew rate, high to low Electrostatic discharge Latch-up Filter delay
Min 2.5 0.1 1.9 -0.5 -0.66 1.1 1.5 200 2.5 100 -
Max 3.5 0.5 7.0 1.0 -0.77 1.3 1.7 400 24 200 625
Units V V V V V V V mV mA mA mA
Test Conditions IOH = 2.5 mA IOL = 48 mA Referenced to VSS VDD = 4.75; II = -20 mA VOH = 2.5 V VOL = 0.5 V Output driving low, pin shorted to VDD supply2 Output driving high, pin shorted to VSS supply -0.5 < VDD < 5.25 VPIN = 2.7 V -0.5 < VDD < 5.25 VPIN = 0.5 V SCSI pins3 PQFP Figure 7-1 Figure 7-1 Figure 7-1 Figure 7-1 MIL-STD-883C; 3015-7 Figure 4-1
VOL VIH VIL VIK VTH VTL IOH
1
VTH-VTL Hysteresis IOL IOSH
1
IOSL
-
95
mA
ILH ILL RI CP tR
1
20 9.7 5.2 0.15 0.19 2 100 10
10 -10 10 18.5 14.7 0.49 0.67 15
A A
M pF ns ns V/ns V/ns KV mA ns
tF dVH/dt dVL/dt ESD
Note: These values are guaranteed by periodic characterization; they are not 100% tested on every device.
1 2 3
Active negation outputs only: Data, Parity, SREQ/, SACK/
Single pin only; irreversible damage may occur if sustained for one second SCSI RESET pin has 10 k pull-up resistor SYM53C120 Data Manual and SYM2010x Boards
4-4
PRELIMINARY
Electrical Characteristics TolerANT Technology Electrical Characteristics
t1
REQ or ACK Input
VTL
Figure 4-1: Rise and Fall Time Test Conditions
1.1
1.3
Received Logic Level
1
0 1.5 1.7
Input Voltage (Volts)
Figure 4-2: Hysteresis of SCSI Receiver
SYM53C120 Data Manual and SYM2010x Boards
4-5
Electrical Characteristics TolerANT Technology Electrical Characteristics
PRELIMINARY
+40
Input Current (milliAmperes)
+20 14.4 V 8.2 V 0 -0.7 V -20 OUTPUT ACTIVE -40 HI-Z
-4
0
4
8
12
16
Input Voltage (Volts)
Figure 4-3: Input Current as a Function of Input Voltage
0
100
Output Sink Current (milliAmperes)
Output Source Current (milliAmperes)
-200
80
60
-400
40
-600
20
-800 0 1 2 3 4 5
0 0 1 2 3 4 5
Output Voltage (Volts)
Output Voltage (Volts)
Figure 4-4: Output Current as a Function of Output Voltage
4-6
SYM53C120 Data Manual and SYM2010x Boards
PRELIMINARY
Electrical Characteristics AC Characteristics
AC Characteristics
The AC characteristics described in this section apply over the entire range of operating conditions (refer to the DC Characteristics section). Chip timings are based on simulation at worst case voltage, temperature, and processing. The SYM53C120 requires a 40 MHz clock input.
Table 4-11: Clock Timing Symbol t1 t2 t3 t4 Parameter Clock period Clock low time Clock high time Clock rise time Min 24.5 10 10 1 Max 25.5 15 15 Units ns ns ns V/ns
t1 t3
CLOCK
t4
t2
Figure 4-5: Clock Timing
SYM53C120 Data Manual and SYM2010x Boards
4-7
Electrical Characteristics AC Characteristics
PRELIMINARY
SCSI Interface Timings
Table 4-12: Input Timings Symbol t1 t2 t3 t4 Parameter Input data setup Input data hold Input REQ/ACK assertion pulse width Input REQ/ACK deassertion pulse width Min 1 6 11 Max Units ns ns ns
16
-
ns
Table 4-13: Output Timings
Symbol t5 t6 t7 t8
Parameter Output data setup Output data hold Output REQ/ACK pulse width REQ/ACK transport delay
Min min [t1 + 17ns, t4+5] max [24, (t2 - 20), t3] max [20 ns, t3 -5] 25 ns if REQ/ACK is clock for input data, 10 ns if not 6
Max max [30 ns, t3 +5] 50 ns if REQ/ACK is clock for input data, 30 ns if not [t3 +35]
Units ns ns ns ns
t9
Data transport delay
ns
4-8
SYM53C120 Data Manual and SYM2010x Boards
PRELIMINARY
Electrical Characteristics AC Characteristics
Input Timings REQ or ACK
t3
t4
t1
t2
Data
Valid Data
Output Timings REQ or ACK
t8
t7
t9
t5
t6
Data
Valid Data
Figure 4-6: Input /Output Timings
SYM53C120 Data Manual and SYM2010x Boards
4-9
Electrical Characteristics AC Characteristics
PRELIMINARY
4-10
SYM53C120 Data Manual and SYM2010x Boards
PRELIMINARY
SYM20101/2 SCSI Bus Boards SYM20101/2 Circuit Board Description
Chapter 5
SYM20101/2 SCSI Bus Boards
SYM20101/2 Circuit Board Description
This chapter describes the SYM20101/2 family of SCSI boards based on the SYM53C120 SCSI Bus Expander chip. The SYM20101 Extender and the SYM20102 Converter are wide (16-bit) SCSI Bus boards. The SYM20101 board connects a single-ended SCSI bus to another single-ended bus. The SYM20102 board connects a single-ended SCSI bus to a differential SCSI bus. These boards provide electrical isolation between two SCSI buses, allowing for increased device connectivity and greater cable distances. The board attaches directly to the SCSI bus; target and initiator devices can be located on either the A bus or the B bus. Supporting SCSI-1, -2 and -3 standards, the boards work with any Symbios Logic SCSI products, as well as any other industry-standard SCSI controllers and devices up to Wide Ultra SCSI with transfer rates of 40 Mbytes/second. The following describes the functions of the circuitry on the SYM20101/2. The heart of the SYM20101 and SYM20102 boards is the SYM53C120 SCSI Bus Expander chip, which is described in Chapters 1 through 4 of this manual. The SYM53C120 chip provides the capability to check SCSI signal tolerances as signals are received and, if necessary, realign them to the SCSI specification. This includes re-timing logic, precision delay control, state machine control and differential control for the SCSI signals. The additional circuitry on the SYM20101/2 boards provide electrical isolation, termination and buffering of the signals. The first part of this chapter describes the common characteristics both boards. The end of this chapter describes the unique characteristics of each board.
Features
s
SCSI Interface
s
s s s s
s s
Two 16-bit SCSI interfaces logically connected through the SYM53C120 Bus Expander chip Active termination on the single-ended buses Remote termination control 68-pin high density connectors Configuration switches and connector for enabling termination power LEDs indicating busy and termination fault Wide Ultra SCSI data transfer capability SYM20101 SCSI Bus Extender board 4.00" X 3.00" SYM20102 SCSI Bus Converter board 3.95" X 4.50"
s
Board Dimensions
s
s
Physical Characteristics
The SYM20101/2 boards are palm-size rectangular boards each with opposing 68-pin connectors, a disk drive type power connector, and a subsystem interface to control termination and indicate busy. The boards are designed to be mounted in an enclosure.
Electrical Characteristics
The SYM20101/2 boards maximum power requirements, including SCSI TERMPWR, under normal operation is:
s
+5V DC 5% 1.1A over the operating range of 5C to 55C
SYM53C120 Data Manual and SYM2010x Boards
5-1
SYM20101/2 SCSI Bus Boards SYM20101/2 Circuit Board Description
PRELIMINARY
Under abnormal conditions such as a short on SCSI TERMPWR, +5V current may be higher. At temperatures of at least 25C a current of 4.0A is sustained no longer than 30 seconds before the self-resetting TERMPWR short circuit protection device opens.
Compatibility
The SCSI interface is compatible with the AMSI standard X3T9.2.
Thermal, Atmospheric Characteristics
The boards are designed to operate in an environment defined by the following parameters:
s s
Operational Characteristics
The SYM20101/2 boards are designed for use in computer systems needing electrical isolation via extension or conversion of the SCSI bus. The operation is logically transparent to software, data, and bus protocol operations. It uses no software code and does not use a SCSI ID. In its simplest form, the SYM53C120 based boards passes data and parity from a source bus to a load bus. The simplest model is that the SYM53C120 is just pieces of wire that allow corresponding SCSI signals to flow from side to side.
Temperature range: 5C to 55C (dry bulb) Relative humidity range: 5% to 90% noncondensing Maximum dew point temperature: 32C Storage Temperature:
s
s s
s
Temperature range: -45C to +105C (dry bulb) 10C per hour Relative Humidity range: 0% to 90% noncondensing
Electromagnetic Compliance
The boards are designed and implemented to minimize electromagnetic emissions, susceptibility, and the effects of electromagnetic discharge. The boards meet the emission requirements of CISPR II, VCCI and FCC Class B as well as the immunity requirements for CE mark and caries the CE logo.
Safety Characteristics
The bare boards meet or exceed the requirements of UL flammability rating 94V0. The bare boards are also marked with the supplier's name or trademark, type, and UL flammability rating. All voltages these boards use are below the SELV 42.4V limit.
Performance Characteristics
The SCSI interface operates at a burst transfer rate of up to 40 MBytes per second for wide SCSI. Actual transfer rates are a function of the subsystem.
5-2
SYM53C120 Data Manual and SYM2010x Boards
PRELIMINARY
SYM20101/2 SCSI Bus Boards SYM20101 SCSI Bus Extender Board
SYM20101 SCSI Bus Extender Board
The SCSI functionality for the SYM20101 Extender board is contained within the SYM53C120 SCSI Bus Expander chip. The SYM20101 physically and electrically connects two single-ended SCSI buses as one logi-
cal SCSI bus, re-generates timing, and passes bus protocol in compliance with the SCSI standard. The SYM20101 board is designed for use in computer systems needing isolation, and/or extension of the SCSI bus. The board requires no software code and does not use a SCSI ID. Figure 5-1 illustrates the component location on the SYM20101 board.
3.00"
SYM20101
CR3
SE-A SE-B BUSY TERM TERM
U4 J3
U 6
J4
SW-1 SW-2 SW-3 SW-4 U5
CR5
CR6
J2
U1
U6
U2
U8 SYM53C120
4.00"
U10
U9
3.75"
SW1 - SE-A TERMPWR SW2 - SE-B TERMPWR SW3 - SE-A TERM OFF SW4 - SE-B TERM OFF
NC GND GND +5V
SE-B
U11
U3
CR3 - SE-B TERMPWR SHORTED CR5 - SE-A BUSY CR6 - SE-A TERMPWR SHORTED
SE-A J1
2.55"
0.125" Dia (x4)
Figure 5-1: SYM20101 SCSI Bus Extender Board
Connectors
s
equivalent)
s
J1 is a standard disk drive power connector. (AMP 641737-1 or equivalent) J2 and J3 are 68-pin, high density, shielded, latching, right-angle SCSI connectors. (AMP 787171-7 or
J4 is a 6-pin unshrouded header. (AMP 104427-4 or equivalent)
s
SYM53C120 Data Manual and SYM2010x Boards
5-3
SYM20101/2 SCSI Bus Boards SYM20101 SCSI Bus Extender Board
PRELIMINARY
Physical Characteristics
The dimensions of the SYM20101 SCSI Bus Extender board are 3.00" x 4.00". Power connection is made through connector J1. SCSI connection is made through high density connectors J2 and J3. Board mounted LEDs or external LED connected to J4 display SCSI bus activity and Termination Power status. Switch pack U4 is combination with external switches connected to J4 control termination. The component height on the top of the board is not greater than 0.5".
SCSI Connectors J2 and J3
The single-ended SCSI interface on the SYM20101 board operates as either an 8-bit or 16-bit, synchronous or asynchronous SCSI bus. The signal definitions conform to the SCSI-2 single-ended standard. The SCSI interface connectors J2 and J3 are both 68-pin high density latching right angle receptacles and the pin definitions conform to the X3T9.2/90-048 single-ended P cable recommendation. SCSI termination power can also be supplied by the board. The following table shows the signal assignments for J2 and J3.
Table 5-2: SE SCSI 68-pin Connectors J2 & J3
Pin Signal Name Pin Signal Name
Board Mounting
The SYM20101 SCSI Bus Extender board is designed to be mounted in an enclosure or computer cabinet. The SYM20101 mounting holes are 0.125 inch in diameter. They are located 2.55" by 3.75" apart in relation to the 3.00" by 4.00" size of the board. The mounting holes are spaced equal distance from the edges of the board.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND TERMPWR TERMPWR No Connect GROUND GROUND GROUND GROUND GROUND GROUND GROUND
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
SD(12) SD(13) SD(14) SD(15) SD(P1) SD(0) SD(1) SD(2) SD(3) SD(4) SD(5) SD(6) SD(7) SD(P0) GROUND GROUND TERMPWR TERMPWR No Connect GROUND SATN GROUND SBSY SACK SRST SMSG
Board Connectors
There are four connectors on the SYM20101 board:
s s s
Power Connector J1 SCSI Connectors J2 and J3 LED and SCSI Terminators Signals J4
Power Connector J1
The DC power interface is designed to receive a standard disk drive type power plug. The Termination Power (TERMPWR) circuitry has a +5V connection through a diode and a vendor-recommended capacitance value of 0.1F. There is a fuse between the +5V connector and the SCSI bus TERMPWR connectors.
Table 5-1: Power Connector J1 J1-Pin Number 1 2 3 4 Signal Name Open Ground Ground +5 Volts
5-4
SYM53C120 Data Manual and SYM2010x Boards
PRELIMINARY
SYM20101/2 SCSI Bus Boards SYM20101 SCSI Bus Extender Board
Table 5-2: SE SCSI 68-pin Connectors J2 & J3
Pin Signal Name Pin Signal Name
necting the Disable SE-A TERM or Disable SE-B TERM pins on J4 to ground turns-off on-board termination on the indicated physical bus. See the following table.
Table 5-4: Termination Control Connector J4 J4-Pin Number 1 2 3 4 Signal Name Disable SE-A TERM Ground Disable SE-B TERM Ground
27 28 29 30 31 32 33 34
GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND
61 62 63 64 65 66 67 68
SSEL SC/D SREQ SI/O SD(8) SD(9) SD(10) SD(11)
LEDs and Connector J4 External Termination Control Connector J4
A-Side and B-Side single-ended termination circuit provides termination for the SCSI buses. On-board termination for each of the two physical busses is controlled in one of two ways: switches or the termination interface (J4). Switches The SYM20101 board contains the following four switches at location U4.
Table 5-3: U4 Switches Switch SW1 Position ON OFF ON SW2 OFF ON SW3 SW4 OFF ON OFF Condition Enable Disabled Enable Disabled Disabled Enabled Disabled Enabled Description A-Side Termination Power B-Side Termination Power A-Side Termination B-Side Termination CR3 CR5 CR6 LED
The SYM20101 board contains three LEDs: one bus activity LED, and two board status LEDs. One green LED indicates SCSI Bus Busy. Two yellow LEDs, one for each bus, indicate when termination power (TERMPWR) is shorted to ground. For instance, if Termination Power is grounded somewhere in the subsystem while Termination power is supplied by the board (when U4 switches SW1 and/or SW2 are enabled).
Table 5-5: LED Description Color/ Condition Yellow/ON Green/ON Yellow/ON Description B-Side, TERMPWR shorted to ground A-Side, BUSY (SCSI active on Side-A) A-Side, TERMPWR shorted to ground
The connector J4, pins 5 and 6, is an LED interface that contains the signal and ground for the SCSI Busy LED. An external LED harness can be connected to the board for external mounting of a SCSI Busy LED.
Table 5-6: LED Connector J4 J4-Pin Number 5 6 Signal Name BUSY LED+ BUSY LED-
Termination Interface The termination control on the SYM20101 board permits the connection of a subsystem harness for external control of the on-board active SCSI terminators. Con-
SYM53C120 Data Manual and SYM2010x Boards
5-5
SYM20101/2 SCSI Bus Boards PRELIMINARY SYM20101 SCSI Bus Extender Board Installation Instructions
SYM20101 SCSI Bus Extender Board Installation Instructions
Software Requirements
There are no software requirements for this board.
Setting Switches
Use the information under the heading Switches or the information on the board to properly set the switches at board location U4.
Connecting Cables
s
Connect power plug to connector J1. Connect SCSI cables to connectors J2 and J3. Connect optional harness to connector J4 for external control of active SCSI terminators using external switches and to view SCSI bus activity on an LED.
Board Mounting
Mount the board inside the selected enclosure using four fasteners in the 0.125" diameter mounting holes.
s s
Optional LED and Control Termination Harness
Mounting hole for fastener
Mounting hole for fastener
SE-A SE-B BUSY TERM TERM
SYM20101
CR3
U4 J3
U 6
J4
SW-1 SW-2 SW-3 SW-4 U5
CR5
CR6
J2
U1
B-Side SCSI SE Connector
U2
U9
U6
A-Side SCSI SE Connector
U10 U11
SW1 - SE-A TERMPWR SW2 - SE-B TERMPWR SW3 - SE-A TERM OFF SW4 - SE-B TERM OFF
U3
SE-B
U8 SYM53C120
NC GND GND +5V
CR3 - SE-B TERMPWR SHORTED CR5 - SE-A BUSY CR6 - SE-A TERMPWR SHORTED
SE-A J1
Mounting hole for fastener
0.125" Dia. Mounting hole for fastener Power Plug
Figure 5-2: SYM20101 Board Installation
5-6
SYM53C120 Data Manual and SYM2010x Boards
PRELIMINARY
SYM20101/2 SCSI Bus Boards SYM20102 SCSI Bus Converter Board
SYM20102 SCSI Bus Converter Board
The SCSI functionality for the SYM20102 Converter board is contained within the SYM53C120 SCSI Bus Expander chip. The SYM20102 physically and electrically connects one single-ended SCSI buses and one differential SCSI bus as one logical SCSI bus, re-gener-
ates timing, and passes bus protocol in compliance with the SCSI standard. The SYM20102 board is designed for use in computer systems needing isolation, and extension or transceiver translation of the SCSI bus. The operation is logically transparent to software and data, uses no software code and does not use a SCSI ID. Figure 5-3 illustrates the component location on the SYM20102 Converter board.
4.50"
SYM20102
CR1
SE DIFF BUSY TERM TERM CR10 CR7
J4 DIFF
SW-1 SW-2 SW-3 SW-4
U 6 U8 U1
SE
U11 SYM53C120
NC GND GND +5V
U7
J1 J3
CR1 - DIFF TERMPWR SHORTED CR7 - BUSY CR10 - SE TERMPWR SHORTED
SW1 - SE TERMPWR SW2 - DIFF TERMPWR SW3 - SE TERM OFF SW4 - DIFF TERM OFF
U14
U3
U6
U13
3.95"
U2
U5
U12
3.75"
J2
2.55"
0.125" Dia (x4)
Figure 5-3: SYM20101 SCSI Bus Converter Board
Connectors
s
right-angle SCSI connectors. (AMP 787171-7 or equivalent)
s
J1 is a standard disk drive power connector. (AMP 641737-1 or equivalent) J2 and J3 are 68-pin high density shielded latching
J4 is a 6-pin unshrouded header. (AMP 104427-4 or equivalent)
s
SYM53C120 Data Manual and SYM2010x Boards
5-7
SYM20101/2 SCSI Bus Boards SYM20102 SCSI Bus Converter Board
PRELIMINARY
Physical Characteristics
The dimensions of the SYM20102 Extender board are 3.95" x 4.50". Power connection is made through connector J1. SCSI connection is made through high density connectors J2 and J3. Board mounted LEDs or external LED connected to J4 display SCSI bus activity and Termination Power status. Switch pack U4 is combination with external switches connected to J4 control termination. The component height on the top of the board is not greater than 0.5".
SCSI Connectors J2 and J3
The SCSI interfaces on the SYM20102 board operates as either an 8-bit or 16-bit, synchronous or asynchronous SCSI bus. The SCSI interface connectors J2 and J3 are both 68-pin high density latching right angle receptacles and the pin definitions conform to the X3T9.2/ 90-048 single-ended P cable recommendation. SCSI termination power can also be supplied by the board. Connector J2 is a single-ended only connector and its pin-out is the same as shown in Table 5-2. The following table shows the signal assignments for J3 which is a single-ended or a differential connection.
Table 5-8: DIFF SCSI 68-pin Connector J3
Pin Signal Name Pin Signal Name
Board Mounting
The SYM20102 Converter board is designed to be mounted in an enclosure or computer cabinet. The SYM20102 mounting holes are 0.125 inch in diameter. They are located 2.55" by 3.75" apart in relation to the 3.95" by 4.50" size of the board. The mounting holes are spaced equal distance from the edges of the board.
1 2 3 4 5 6 7 8 9
+DB(12) +DB(13) +DB(14) +DB(15) +DB(P1) +DB(0) +DB(1) +DB(2) +DB(3) +DB(4) +DB(5) +DB(6) +DB(7) +DB(P0) GROUND DIFFSENS TERMPWR TERMPWR RESERVED GROUND +ATN GROUND +BSY +ACK +RST
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
-DB(12) -DB(13) -DB(14) -DB(15) -DB(P1) -DB(0) -DB(1) -DB(2) -DB(3) -DB(4) -DB(5) -DB(6) -DB(7) -DB(P0) GROUND GROUND TERMPWR TERMPWR RESERVED GROUND -ATN GROUND -BSY -ACK -RST
Board Connectors
There are four connectors on the SYM20102 board:
s s s
Power Connector J1 SCSI Connectors J2 and J3 LED and SCSI Terminators Signals J4
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Power Connector J1
The DC power interface is designed to receive a standard disk drive type power plug. The Termination Power (TERMPWR) circuitry has a +5V connection through a diode and a vendor-recommended capacitance value of 0.1F. There is a fuse between the +5V connector and the SCSI bus TERMPWR connectors.
Table 5-7: Power Connector J1 J1-Pin Number 1 2 3 4 Signal Name Open Ground Ground +5 Volts
5-8
SYM53C120 Data Manual and SYM2010x Boards
PRELIMINARY
SYM20101/2 SCSI Bus Boards SYM20102 SCSI Bus Converter Board
Table 5-8: DIFF SCSI 68-pin Connector J3
Pin Signal Name Pin Signal Name
necting the Disable SE-A TERM or Disable SE-B TERM pins on J4 to ground turns-off on-board termination on the indicated physical bus. See the following table.
Table 5-10: Termination Control Connector J4 J4-Pin Number 1 2 3 4 Signal Name Disable SE-A TERM Ground Disable SE-B TERM Ground
26 27 28 29 30 31 32 33 34
+MSG +SEL +C/D +REQ +I/O +D(8) +D(9) +D(10) +D(11)
60 61 62 63 64 65 66 67 68
-MSG -SEL -C/D -REQ -I/O -D(8) -D(9) -D(10) -D(11)
LEDs and Connector J4
The SYM20102 board contains three LEDs: one bus activity LED and two board status LEDs. One green LED indicates SCSI bus busy. Two yellow LEDs, one for each bus, indicate when termination power (TERMPWR) is shorted to ground. For instance, if Termination Power is grounded somewhere in the subsystem while Termination power is supplied by the board (when U8 switches SW1 and/or SW2 are enabled).
Table 5-11: LED Description LED Color/ Condition Yellow/ON Green/ON Yellow/ON Description B-Side, TERMPWR shorted to ground A-Side, BUSY (SCSI active on Side-A) A-Side, TERMPWR shorted to ground
External Termination Control Connector J4
A-Side and B-Side single-ended termination circuit provides termination for the SCSI buses. On-board termination for each of the two physical busses is controlled in one of two ways: switches or the termination interface (J4). Switches The SYM20102 board contains the following four switches at location U8.
Table 5-9: U8 Switches Switch SW1 Position ON OFF ON SW2 OFF ON SW3 SW4 OFF ON OFF Condition Enable Disabled Enable Disabled Disabled Enabled Disabled Enabled Description A-Side Termination Power B-Side Termination Power A-Side Termination B-Side Termination
CR1 CR7 CR10
The connector J4, pins 5 and 6, is an LED interface that contains the signal and ground for the SCSI Busy LED. An external LED harness can be connected to the board for external mounting of a SCSI Busy LED.
Table 5-12: LED Connector J4 J4-Pin Number 5 6 Signal Name BUSY LED+ BUSY LED-
Termination Interface The termination control on the SYM20101 board permits the connection of a subsystem harness for external control of the on-board active SCSI terminators. Con-
SYM53C120 Data Manual and SYM2010x Boards
5-9
SYM20101/2 SCSI Bus Boards PRELIMINARY SYM20102 SCSI Bus Converter Board Installation Instructions
SYM20102 SCSI Bus Converter Board Installation Instructions
Software Requirements
There are no software requirements for this board.
Setting Switches
Use the information under the heading Switches or the information on the board to properly set the switches at board location U8.
Connecting Cables
s
Connect power plug to connector J1. Connect SCSI cables to connectors J2 and J3. Connect optional harness to connector J4 for external control of active SCSI terminators using external switches and to view SCSI bus activity on an LED.
Board Mounting
Mount the board inside the selected enclosure using four fasteners in the provided mounting holes. Make sure nothing touches any of the board's electrical components that might short them out.
s s
Optional LED and Active Termination Harness
Mounting hole for fastener
Mounting hole for fastener
SE DIFF BUSY TERM TERM CR10 CR7
CR1
SYM20102
J5 DIFF
SW-1 SW-2 SW-3 SW-4
U 6 U8 U1
SE
U2
U11 SYM53C120
NC GND GND +5V
U7
J1 J3
CR1 - DIFF TERMPWR SHORTED CR7 - BUSY CR10 - SE TERMPWR SHORTED
SW1 - SE TERMPWR SW2 - DIFF TERMPWR SW3 - SE TERM OFF SW4 - DIFF TERM OFF
U14
U3
U6
U13
Differential SCSI Connector
U12
U5
SCSI Single-Ended Connector
J2
Mounting hole for fastener Power Plug
0.125" Dia. Mounting hole for fastener
Figure 5-4: SYM20102 Board Installation
5-10
SYM53C120 Data Manual and SYM2010x Boards
PRELIMINARY
Mechanical Drawings SYM53C120 Mechanical Drawing
Appendix A
Mechanical Drawings
SYM53C120 Mechanical Drawing
The SYM53C120 comes in a 128-pin metric Plastic Quad Flat Package (PQFP) with a 3.9 mm footprint.
23.9 mm 20.0 mm
0.50 mm
17.9 mm 14.0 mm
128-Pin PQFP
Pin 1
0 Min 2.80 0.25 0 - 7 0.13 mm 0.40 Min 0.80 0.15 1.95 Note: All dimensions are in millimeters 0.22 0.05 SEATING PLANE 3.40 Max
Figure A-1: SYM53C120 Mechanical Drawing
SYM53C120 Data Manual and SYM2010x Boards
A-1
Mechanical Drawings SYM53C120 Mechanical Drawing
PRELIMINARY
A-2
SYM53C120 Data Manual and SYM2010x Boards
PRELIMINARY
Differential Wiring Diagram SYM53C120 Differential Wiring Diagram
Appendix B
Differential Wiring Diagram
SYM53C120 Differential Wiring Diagram
Figure B-1 shows the wiring diagram for Ultra SCSI operation in the differential mode using pull-up resistors.
SYM53C120 SCSI B DIFF Control B_SELDIR B_BSYDIR B_RSTDIR B_REQDIR B_ACKDIR B_MSGDIR B_CD_DIR B_IO_DIR B_ATNDIR B_SSEL/ B_SBSY/ B_SRST/ B_SREQ/ B_SACK/ B_SMSG/ B_SCD/ B_SIO/ B_SATN/ SN75976A2 VDD 1.5K ohm B_SSEL/ B_SELDIR B_SBSY/ B_BSYDIR B_SRST/ B_RSTDIR B_SREQ/ B_REQDIR B_SACK/ B_ACKDIR B_SMSG/ B_MSGDIR B_SCD/ B_CD_DIR B_SIO/ B_IO_DIR B_SATN/ B_ATNDIR CDE0 CDE1 CDE2 BSR CRE/ 1A 1DE/RE/ 2A 2DE/RE/ 3A 3DE/RE/ 4A 4DE/RE/ 5A 5DE/RE/ 6A 6DE/RE/ 7A 7DE/RE/ 8A 8DE/RE/ 9A 9DE/RE/
1B+ 1B2B+ 2B3B+ 3B4B+ 4B5B+ 5B6B+ 6B7B+ 7B8B+ 8B9B+ 9B-
-SEL +SEL -BSY +BSY -RST +RST -REQ +REQ -ACK +ACK -MSG +MSG -C/D +C/D -I/O +I/O -ATN +ATN
VDD 1.5K ohm B_SDIRP1 B_SDIR15 B_SDIR14 B_SDIR13 B_SDIR12 B_SDIR11 B_SDIR10 B_SDIR09 B_SDIR08 B_SDP1/ B_SD15/ B_SD14/ B_SD13/ B_SD12/ B_SD11/ B_SD10/ B_SD09/ B_SD08/ B_SD08/ B_SDIR08 B_SD09/ B_SDIR09 B_SD10/ B_SDIR10 B_SD11/ B_SDIR11 B_SD12/ B_SDIR12 B_SD13/ B_SDIR13 B_SD14/ B_SDIR14 B_SD15/ B_SDIR15 B_SDP1/ B_SDIRP1
SN75976A2 CDE0 CDE1 CDE2 -DB0 (4) 1B+ BSR +DB0 (3) 1BCRE/ -DB1 (6) 2B+ 1A +DB1 (5) 2B1DE/RE/ -DB2 (8) 3B+ 2A +DB2 (7) 3B2DE/RE/ -DB3 (10) 4B+ 3A +DB3 (9) 4B3DE/RE/ -DB4 (12) 5B+ 4A +DB4 (11) 5B4DE/RE/ -DB5 (14) 5A 6B+ +DB5 (13) 6B5DE/RE/ -DB6 (16) 7B+ 6A +DB6 (15) 7B6DE/RE/ -DB7 (18) 8B+ 7A +DB7 (17) 8B7DE/RE/ -DBP (20) 9B+ 8A +DBP (19) 9B8DE/RE/ 9A 9DE/RE/ SN75976A2 CDE0 CDE1 CDE2 BSR 1B+ CRE/ 1B1A 2B+ 1DE/RE/ 2B2A 3B+ 2DE/RE/ 3B3A 4B+ 4B3DE/RE/ 4A 5B+ 4DE/RE/ 5B6B+ 5A 5DE/RE/ 6B7B+ 6A 7B6DE/RE/ 7A 8B+ 7DE/RE/ 8B8A 9B+ 8DE/RE/ 9B9A 9DE/RE/ DIFFSENS Control Logic
SCSI BUS
VDD 1.5K ohm B_SDIRP0/ B_SDIR7/ B_SDIR6/ B_SDIR5/ B_SDIR4/ B_SDIR3/ B_SDIR2/ B_SDIR1/ B_SDIR0/ B_SDP0/ B_SD7/ B_SD6/ B_SD5/ B_SD4/ B_SD3/ B_SD2/ B_SD1/ B_SD0/ DIFFSENS B_SD0/ B_SDIR0/ B_SD1/ B_SDIR1/ B_SD2/ B_SDIR2/ B_SD3/ B_SDIR3/ B_SD4/ B_SDIR4/ B_SD5/ B_SDIR5/ B_SD6/ B_SDIR6/ B_SD7/ B_SDIR7/ B_SDP0/ B_SDIRP0/
-DB0 (4) +DB0 (3) -DB1 (6) +DB1 (5) -DB2 (8) +DB2 (7) -DB3 (10) +DB3 (9) -DB4 (12) +DB4 (11) -DB5 (14) +DB5 (13) -DB6 (16) +DB6 (15) -DB7 (18) +DB7 (17) -DBP (20) +DBP (19)
Figure B-1: SYM53C120 Differential Wiring Diagram
SYM53C120 Data Manual and SYM2010x Boards B-1
Differential Wiring Diagram SYM53C120 Differential Wiring Diagram
PRELIMINARY
B-2
SYM53C120 Data Manual and SYM2010x Boards
PRELIMINARY
Glossary
Glossary
ACK/ Acknowledge - Driven by an initiator, ACK/ indicates an acknowledgment for a SCSI data transfer. In the target mode, ACK/ is received as a response to the REQ/ Signal. ANSI American National Standards Institute. Arbitration The process of selecting one respondent from a collection of several candidates that request service concurrently. Asserted A signal is asserted when it is in the state which is indicated by the name of the signal. Opposite of negated or de-asserted. Assertion The act of driving a signal to the true state. Asynchronous Transmission Transmission in which each byte of the information is synchronized individually, through the use of Request (REQ/) and Acknowledge (ACK/) signals. ATN/ Attention - Driven by an initiator, indicates an attention condition. In the target role, ATN/ is received and is responded to by entering the Message Out Phase. Auto-configuration Ports Three 8-bit ports (Address, Write_Data, and Read_Data) used by software to access the configuration space on each Plug and Play card. The configuration space is implemented as a set of 8-bit registers. These registers are used by the Plug and Play software to issue commands, check status, access the resource data information, and configure the Plug and Play hardware.
Block A block is the basic 512 byte region of storage into which the storage media is divided. The Logical Block Address protocol uses sequential block addresses to access the media. BSY/ Busy - Indicates that the SCSI Bus is being used. BSY/ can be driven by both the initiator and the target device. Bus A collection of unbroken signal lines that interconnect computer modules. The connections are made by taps on the lines. C_D/ Control/Data - Driven by a target, indicates Control or Data Information is on the SCSI Bus. This signal is received by the initiator. Connect The function that occurs when an initiator selects a target to start an operation, or a target reselects an initiator to continue an operation. Control Signals The set of nine lines used to put the SCSI bus into its different phases. The combinations of asserted and negated control signals define the phases. Controller A computer module that interprets signals between a host and a peripheral device. Often, the controller is a part of the peripheral device, such as circuitry on a disk drive. DB0/-DB7/ SCSI Data Bits and Parity Bit - These eight Data Bits (DB0/-DB7/), plus a Parity Bit (DBP/), form the SCSI Bus. DB7/ is the most significant bit and has the highest priority ID during the Arbitration
SYM53C120 Data Manual and SYM2010x Boards
Glossary-1
PRELIMINARY
Glossary
Phase. Data parity is odd. Parity is always generated and optionally checked. Parity is not valid during arbitration. De-asserted The act of driving a signal to the false state or allowing the cable terminators to bias the signal to the false state (by placing the driver in the high impedance condition). A signal is de-asserted or negated when it is in the state opposite to that which is indicated by the name of the signal. Opposite of asserted. Device A single unit on the SCSI bus, identifiable by an SCSI address. It can be a processor unit, a storage unit (such as a disk or tape controller or drive), an output unit (such as a controller or printer), or a communications unit. Disconnect The function that occurs when a target releases control of the SCSI bus, allowing the bus to go to the Bus Free phase. Driver When used in the context of electrical configuration, "driver" is the circuitry that creates a signal on a line. When used in the context of software, "driver" is the program that translates commands between the initiator and target. External Configuration All SCSI peripheral devices are external to the host enclosure. External Terminator The terminator that exists on the last peripheral subsystem that terminates the external end of the SCSI bus. Exit-Point Terminator A Terminator that may be enabled or disabled which exists at the 50-position high-density connector on hosts that support a mixed configuration (combination of internal and external SCSI peripheral devices).
Free In the context of Bus Free phase, "free" means that no SCSI device is actively using the SCSI bus and, therefore, the bus is available for use. Gigabyte One billion bytes; equal to one thousand megabytes. High (logical level) A signal is in the high logic state when it is above approximately 2.5 volts. Host A processor, usually consisting of the central processing unit and main memory. Typically, a host communicates with other devices, such as peripherals and other hosts. On the SCSI bus, a host has an SCSI address. Host Adapter Circuitry that translates between a processor's internal bus and a different bus, such as SCSI. On the SCSI bus, a host adapter usually acts as an initiator. Initiator An SCSI device that requests another SCSI device (a target) to perform an operation. Usually, a host acts as an initiator and a peripheral device acts as a target. Internal Configuration All SCSI peripheral devices are internal to the host enclosure. Internal Terminator The terminator that exists within the host that terminates the internal end of the SCSI bus. I/O/ Input/Output - Driven by a target, controls the direction of data transfer on the SCSI Bus. When active, this signal indicates input to the initiator. When inactive, this signal indicates output from the initiator. This signal is also used to distinguish between the Selection and Reselection Phases.
Glossary-2
SYM53C120 Data Manual and SYM2010x Boards
PRELIMINARY
Glossary
I/O Cycle An I/O cycle is an Input (I/O Read) operation or Output (I/O Write) operation that accesses the PC Card's I/O address space. I/O Mapped A storage location or register is I/O mapped when it is available to be accessed using I/O cycles. The register or storage location might also be accessible using memory cycles, in which case it would also be memory mapped. IREQ Interrupt Request - Alerts the host computer of a condition that needs to be serviced. Most of the interrupts are individually maskable. The Interrupt Request signal between a PC Card and a socket when the I/O interface is active. LBA Abbreviation for Logical Block Address. Logical Block Address A logical block address is a sequential address for accessing the blocks on the storage media. The first block of the media is addressed as block 0 and succeeding blocks are numbered sequentially until the last block is encountered. This is the traditional method for accessing peripherals on an SCSI interface bus. Logical Unit The logical representation of a physical or virtual device, addressable through a target. A physical device can have more than one logical unit. Low (logical level) A signal is in the low logic level when it is below approximately 0.5 volts. LSB Abbreviation for Least Significant Bit or Least Significant Byte. That portion of a number, address or field that occurs right-most when its value is written as a single number in conventional hexadecimal or binary notation. The portion of the number having the least weight in a mathematical calculation using the value.
LUN Logical Unit Number. Used to identify a logical unit. Mandatory A characteristic or feature that must be present in every implementation of the standard. Memory Cycle A memory cycle is a memory read (using Output Enable) operation or memory write (using Write Enable / Program) operation that accesses the PC Card's common memory or attribute memory address space. Memory Interface The memory interface is the default interface after power-up, PCMCIA Hard Reset, and PCMCIA Soft Reset for both PCMCIA cards and sockets. This interface supports memory operations as defined in PCMCIA Release 1.0 and later and is used by both Memory Cards and I/O Cards. Memory Mapped A storage location or register is memory mapped when it is available to be accessed using memory cycles. The register or storage location might also be accessible using I/O cycles, in which it would also be I/O mapped. MHz MegaHertz - Measurement in thousands of cycles per second. Used as a measurement of data transfer rate. microsecond (s) One millionth of a second. MSB Abbreviation for Most Significant Bit and Most Significant Byte. That portion of a number, address or field that occurs left-most when its value is written as a single number in conventional hexadecimal or binary notation. The portion of the number having the most weight in a mathematical calculation using the value. MSG/ Message - Driven active by a target during the Message Phase. This signal is received by the initiator.
SYM53C120 Data Manual and SYM2010x Boards
Glossary-3
PRELIMINARY
Glossary
nanosecond (ns) One billionth of a second. Negated A signal is negated or de-asserted when it is in the state opposite to that which is indicated by the name of the signal. Opposite of asserted. Negation The act of driving a signal to the false state or allowing the cable terminators to bias the signal to the false state (by placing the driver in the high impedance condition). ns nanoseconds. PC Abbreviation for Personal Computer. Often used to refer to an 80x86 based computer system. Parity A method of checking the accuracy of binary numbers. An extra bit, called a parity bit, is added to a number. If even parity is used, the sum of all 1s in the number and its corresponding parity is always even. If odd parity is used, the sum of the 1s and the parity bit is always odd. Peripheral device A device that can be attached to an SCSI bus. Typical peripheral devices are disk drives, tape drives, printers, CD ROMs, or communications units. Phase One of the eight states to which the SCSI bus can be set. During each phase, different communication tasks can be performed. Plug and Play (PnP) Plug and Play is a specification that frees users from locating and setting ID and IRQ switches and jumpers. PnP permits a card to be configured automatically after installation. Port A connection into a bus. The SCSI bus allows eight ports.
Priority The ranking of the devices on the bus during arbitration. Protocol A convention for data transmission that encompasses timing control, formatting, and data representation. Receiver The circuitry that receives electrical signals on a line. Reconnect The function that occurs when a target reselects an initiator to continue an operation after a disconnect. Release The act of allowing the cable terminators to bias the signal to the false state (by placing the driver in the high impedance condition). REQ/ Request - Driven by a target, indicates a request for an SCSI data-transfer handshake. This signal is received by the initiator. Reselect A target can disconnect from an initiator in order to perform a time-consuming function, such as a disk seek. After performing the operation, the target can "reselect" the initiator. RESET Reset - Clears all internal registers when active. It does not assert the SCSI RST/ signal and therefore does not reset the SCSI bus. RST Reset - Indicates an SCSI Bus reset condition. SCSI Address The octal representation of the unique address (07) assigned to an SCSI device. This address is normally assigned and set in the SCSI device during system installation. SCSI ID (Identification) or SCSI Device ID The bit-significant representation of the SCSI address referring to one of the signal lines DB0/ through DB7/.
Glossary-4
SYM53C120 Data Manual and SYM2010x Boards
PRELIMINARY
Glossary
SCSI Small Computer System Interface. SCAM An acronym for SCSI Configured AutoMagically or SCSI Configured AutoMatically. SCAM is SCSI's new automatic ID assignment protocol. SCAM frees SCSI user's from locating and setting SCSI ID switches and jumpers. SCAM is the key part of Plug and Play SCSI. SEL/ Select - Used by an initiator to select a target or by a target to reselect an initiator. Single-ended configuration An electrical signal configuration that uses a single line for each signal, referenced to a ground path common to the other signal lines. The advantage of a single-ended configuration is that it uses half the pins, chips, and board area that differential configurations require. The main disadvantage of singleended configurations is that they are vulnerable to common mode noise. Also, cable lengths are limited. Synchronous transmission Transmission in which the sending and receiving devices operate continuously at the same frequency and are held in a desired phase relationship by correction devices. For buses, synchronous transmission is a timing protocol that uses a master clock and has a clock period. Target An SCSI device that performs an operation requested by an initiator. Termination The electrical connection at each end of the SCSI bus, composed of a set of resistors. s Microsecond.
SYM53C120 Data Manual and SYM2010x Boards
Glossary-5
PRELIMINARY
Glossary
Glossary-6
SYM53C120 Data Manual and SYM2010x Boards
PRELIMINARY
Index
Index
Symbols
s, Glossary-5
B
B_ACKDIR, 2-4, 3-5 B_ATNDIR, 2-4, 3-5 B_BSYDIR, 2-4, 3-5 B_CD_DIR, 2-4, 3-5 B_IO_DIR, 2-4, 3-5 B_MSGDIR, 2-4, 3-5 B_REQDIR, 2-4, 3-5 B_RSTDIR, 2-4, 3-5 B_SACK/, 2-3, 3-4 B_SATN/, 2-4, 3-4 B_SBSY/, 2-3, 3-4 B_SCD/, 2-4, 3-4 B_SD/(15-0), 3-4 B_SDIR(15-0), 3-5 B_SDIR(15-0, P0, P1), 2-4 B_SDIRP(1-0), 3-5 B_SDP/(1-0), 3-4 B_SELDIR, 2-4, 3-5 B_SIO/, 2-4, 3-4 B_SMSG/, 2-4, 3-4 B_SREQ/, 2-3, 3-4 B_SRST/, 2-4, 3-4 B_SSEL/, 2-4, 3-4 Balanced duty cycles, 2-2 Bi-directional connections, 2-1 Block, Glossary-1 Board Connectors, 5-4, 5-8 Board Dimensions, 5-1 Board Mounting, 5-4, 5-8 BSY, Glossary-1 Bus, Glossary-1 Bus arbitration, 3-3, 3-4 Bus Reset, 3-4 Bus timings, 2-2 Busy (BSY), 2-3
Numerics
68-pin connectors, 5-1
A
A_SACK/, 2-3, 3-3 A_SATN/, 2-4, 3-3 A_SBSY/, 2-3, 3-3 A_SCD/, 2-4, 3-3 A_SD/(15-0), 3-3 A_SDP/(1-0), 3-3 A_SIO/, 3-3 A_SMSG/, 2-4, 3-3 A_SREQ/, 2-3, 3-3 A_SRST/, 2-4, 3-3 A_SSEL/, 2-4, 3-3 Absolute Maximum Stress Ratings, 4-1 AC characteristics, 4-7 ACK, 2-3, Glossary-1 Acknowledge, 2-1 Acknowledge (ACK), 2-3 Active negation, 2-1 Active SCSI Terminators Signals, 5-4 Active termination, 5-1 ANSI, Glossary-1 ANSI Standard X3. 131, 2-2 Application examples, 1-2 Arbitration, Glossary-1 Asserted, Glossary-1 Assertion, Glossary-1 Asynchronous, 1-1 Asynchronous transmission, Glossary-1 ATN, Glossary-1 Attention, 3-3, 3-4 Attention (ATN), 2-4
SYM53C120 Data Manual and SYM2010x Boards
Index-1
PRELIMINARY
Index
Busy LED, 5-5, 5-9
C
C_D, Glossary-1 Calibration, 2-2 Capacitance, 4-3 Card Information Structure, Glossary-1 CCS, Glossary-1 CE logo, 5-2 Chip Reset (RESET/), 2-5 CISPR II, 5-2 CLOCK, 3-6 Clock (CLOCK), 2-5 Clock signal, 2-3 Clock Timing, 4-7 Compatibility, 5-2 Configuration, 1-3, 1-4 Configurations, 1-2 Connect, Glossary-1 Connect Cables, 5-6, 5-10 Connectors, 5-3, 5-7 Control Signals, 4-3, Glossary-1 Control/Data (C/D), 2-4 Controller, Glossary-1
Differential Mode (Diff_Mode), 2-5 Differential Sense (Diff_Sense), 2-5 Differential Signals, 4-3 Dimensions, 5-4, 5-8 Disable SE-A TERM, 5-5 Disable SE-B TERM, 5-5 Disconnect, Glossary-2 Double clocking of data, 2-1 Driver, Glossary-2 Driver direction control, 3-5
E
EEPROM, Glossary-2 Electrical Characteristics, 4-1, 5-1 Electromagnetic Compliance, 5-2 Electrostatic discharge, 4-1 Enable/disable SCSI transfers, 3-6 ESD, 4-1 External differential transceiver, 2-4 External SCSI bus, 1-4 External Termination Control Connector, 5-5, 59
F
Fault, 5-5 FCC Class B, 5-2 Filter edges, 2-3 Flammability rating, 5-2 Free, Glossary-2
D
D0-D7, Glossary-1 Data, 2-1, 2-2, 3-4 Data handshake, 3-3, 3-4 Data parity bits, 3-4 DB0-DB7, Glossary-1 DC Characteristics, 4-1 De-asserted, Glossary-2 Decoupling capacitor, 3-1 Delay settings, 2-2 Device, Glossary-2 DIFF SCSI 68-pin Connector, 5-8 DIFF_MODE, 3-6 Diff_Mode Control Signal Polarity, 2-5 DIFF_SENSE, 3-6 Diff_Sense, 3-6 Diff_Sense Control Signal Polarity, 2-5 Differential control, 2-1 Differential Direction Controls, 2-4
G
Gigabyte, Glossary-2 Glitches, 2-2 Glossary, Glossary-1 Green LED, 5-5, 5-9
H
High (logical level), Glossary-2 Host, Glossary-2 Host Adapter, Glossary-2 Hysteresis, 2-2 Hysteresis of SCSI Receiver, 4-5
I
I/O, Glossary-2
Index-2
SYM53C120 Data Manual and SYM2010x Boards
PRELIMINARY
Index
I/O Cycle, Glossary-3 I/O Mapped, Glossary-3 Identification, Glossary-4 Initiator, Glossary-2 Input and Output Timings, 4-8 Input capacitance of I/O pads, 4-3 Input capacitance of input pads, 4-3 Input Current as a Function of Input Voltage, 4-6 Input high voltage, 4-2 Input low voltage, 4-2 Input Signals, 4-2 Input Voltage, 4-1 Input/Output (I/O), 2-4 Internal SCSI bus, 1-4 Internal split ground system, 3-1 IREQ, Glossary-3
MSG, Glossary-3
N
nanosecond, Glossary-4 Negated, Glossary-4 Negation, Glossary-4 ns, Glossary-4
O
Operating Conditions, 4-1 Operating free air, 4-1 Operational Characteristics, 5-2 Output Current as a Function of Output Voltage, 4-6 Output high voltage, 4-2 Output low voltage, 4-2
L
Latch-up current, 4-1 LBA, Glossary-3 Leading edge filter, 2-4 Leading edge filtered, 2-3 LED, 5-1, 5-4, 5-8 LED Description, 5-5, 5-9 Lload bus, 2-1 Load bus, 2-3 Logical Block Address, Glossary-3 Logical Unit, Glossary-3 Low (logical level), Glossary-3 LSB, Glossary-3 LUN, Glossary-3
P
Parallel function, 2-3, 2-4 Parity, 2-1, 2-2, Glossary-4 PC, Glossary-4 Performance Characteristics, 5-2 Peripheral device, Glossary-4 Phase, Glossary-4 Phase line, 3-3, 3-4 Physical Characteristics, 5-4, 5-8 Physical Environment, 5-4, 5-8 Plastic Quad Flat Pack (PQFP), 3-1 Port, Glossary-4 Power Connector, 5-4, 5-8 Power On Reset (POR), 2-5 Power-down, 2-2 Power-up, 2-2 Precision delay control, 2-1 Precision delay control block, 2-2 Precision delay elements, 2-2 Priority, Glossary-4 Protocol, Glossary-4 Pull-down, 2-3, 2-4 Pull-up, 2-3, 2-4 Pulse width, 2-3
M
Mandatory, Glossary-3 Master reset, 3-6 Maximum dew point temperature, 5-2 Memory Cycle, Glossary-3 Memory Interface, Glossary-3 Memory Mapped, Glossary-3 Message (MSG), 2-4 MHz, Glossary-3 microsecond, Glossary-3 Mount Board, 5-6, 5-10 MSB, Glossary-3
R
RC-type input filters, 2-1 Receiver, Glossary-4
SYM53C120 Data Manual and SYM2010x Boards
Index-3
PRELIMINARY
Index
Receiver latch, 2-3 Reconnect, Glossary-4 Recovery, 2-4 Relative Humidity range, 5-2 Relative humidity range, 5-2 Release, Glossary-4 Reliability issue, 2-1 Remote termination, 5-1 REQ, 2-3, Glossary-4 Request, 2-1 Request (REQ), 2-3 Reselect, Glossary-4 Reserved, Glossary-4 RESET, 2-5, Glossary-4 Reset (RST), 2-4 RESET/, 3-6 RESET/ Control Signal Polarity, 2-5 Re-timing, 2-3 Re-timing circuit, 2-1 Re-timing logic block, 2-2 Rise and Fall Time Test Conditions, 4-5 RST, Glossary-4
S
Safety Characteristics, 5-2 Scalable device connectivity, 1-2 SCAM support, 2-4 SCSI, Glossary-5 TolerANT technology, 2-1 SCSI A Signal Description, 3-3 SCSI Address, Glossary-4 SCSI A-side, 1-1, 2-2 SCSI B-side, 1-1, 2-2 SCSI bus disable mode, 1-1, 1-2 SCSI bus electrical isolation, 1-1, 1-4 SCSI bus free state, 2-6 SCSI bus protocol, 2-2, 2-4 SCSI Busy LED, 5-5, 5-9 SCSI Connectors, 5-4, 5-8 SCSI Connectors J2 and J3, 5-4, 5-8 SCSI Device ID, Glossary-4 SCSI I/O logic, 2-4 SCSI ID, 1-1, 5-2, 5-3, 5-7, Glossary-4 SCSI Interface Timings, 4-8
SCSI phases, 2-2 SCSI Signals, 4-2 SCSI Terminators Signals, 5-8 SEL, 2-4, Glossary-5 Select (SEL), 2-3, 2-4 Set Switches, 5-6, 5-10 Signal Descriptions, 3-1 Signal groupings, 2-2 Signal skew, 2-1 Single-ended configuration, Glossary-5 Single-ended control blocks, 2-1 Single-ended to differential, 1-1, 1-3, 2-2 Single-ended to single-ended, 1-1, 1-3, 2-1 Software, 1-1, 2-1 Software Requirements, 5-6, 5-10 Source bus, 2-1, 2-3 State, 2-4 State machines, 2-3 State-machine control, 2-1 State-machine controls, 2-2 Storage Temperature, 5-2 Storage temperature, 4-1 Supply voltage, 4-1 Switches, 5-5, 5-9 SYM20101 Board Installation, 5-6 SYM20101 Extender, 5-1 SYM20101 Extender board, 5-3 SYM20102 Board Installation, 5-10 SYM20102 Converter, 5-1 SYM20102 Converter board, 5-7 SYM2010x Boards, 5-1 SYM2010x family of SCSI boards, 5-1 SYM53C120 Block Diagram, 2-1 SYM53C120 Functional Signal Grouping, 3-2 SYM53C120 Pin Diagram, 3-1 SYM53C120 SCSI Buddy, 1-1 SYM53C120 Signal Grouping, 2-2 Synchronous, 1-1 Synchronous transmission, Glossary-5
T
Target, Glossary-5 Temperature, 2-2 Temperature range, 5-2
Index-4
SYM53C120 Data Manual and SYM2010x Boards
PRELIMINARY
Index
Termination, Glossary-5 Termination Control Connector, 5-5 Termination Interface, 5-5, 5-9 TERMINATION POWER, 5-5 TERMPWR, 5-1, 5-8 Thermal resistance, 4-1 Thermal, Atmospheric Characteristics, 5-2 TolerANT receiver technology, 2-1 TolerANT SCSI, 2-2 TolerANT Technology, 2-1 Benefits, 2-2 Electrical characteristics, 4-4 TolerANT(R) Drivers and Receivers, 2-1 TolerANT(R) technology, 1-2, 2-1 Tri-state, 2-3 Tri-state leakage, 4-2 Typical applications, 1-2
Y
Yellow LEDs, 5-5, 5-9
U
UL flammability rating, 5-2 Ultra SCSI bus, 1-2
V
VCCI, 5-2 VDD_CORE, 3-6 VDD_IO, 3-6 VDD-SCSI, 3-6 Vendor unique, Glossary-5 Voltage, 2-2 VSS_CORE, 3-6 VSS_IO, 3-6 VSS-SCSI, 3-6
W
Warm Start Enable and Transfer Active (WS_ENABLE and XFER_ACTIVE), 2-6 Wide Ultra SCSI, 1-1, 2-1, 5-1 WS_ENABLE, 2-6, 3-6 WS_ENABLE Signal Polarity, 2-6
X
XFER_ACTIVE, 2-6, 3-6 XFER_ACTIVE Signal Polarity, 2-6
SYM53C120 Data Manual and SYM2010x Boards
Index-5
PRELIMINARY
Index
Index-6
SYM53C120 Data Manual and SYM2010x Boards
Symbios Logic Sales Locations
For literature on any Symbios Logic product or service, call our hotline toll-free 1-800-856-3093
North American Sales Locations
Western Sales Area 1731 Technology Drive, Suite 610 San Jose, CA 95110 (408) 441-1080 3300 Irvine Avenue, Suite 255 Newport Beach, CA 92660 (714) 474-7095 Eastern Sales Area 8000 Townline Avenue, Suite 209 Bloomington, MN 55438-1000 (612) 941-7075 12377 MERIT DRIVE, Suite 400 Dallas, TX 75251 (972) 503-3205 92 Montvale Avenue, Suite 3500 Stoneham, MA 02180-3623 (781) 438-0043 30 Mansell Court, Suite 220 Roswell, GA 30076 (404) 641-8001
International Sales Locations
European Sales Headquarters Westendstrasse 193\III 80686 Muenchen Germany 011-49-89-547470-0 Asia/Pacific Sales Headquarters No. 6 Raffles Boulevard #02-256 Marina Square Singapore 039594 011-65-337594
(c) Symbios Logic Inc. Printed in the U.S.A. T14971I 0897-2MH
SYM53C120 SCSI Bus Expander & SYM2010x Boards Version 3.0
Symbios Logic

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